The present disclosure relates to a technique for generating a low-noise bias voltage and a low-noise bias current.
A transceiver circuit for use in wireless communications devices, for example, is required to exhibit strict low-noise characteristics to achieve excellent sensitivity performance. A circuit comprised of CMOS transistors, however, often generates a so-called “flicker noise,” which constitutes a major obstacle to reducing the noise to a desired low level. The flicker noise is inevitably generated in such a structure where a current flows through an interface between silicon and an oxide film, because carriers are randomly trapped by, or released from, lattice defects existing on the interface. The flicker noise is generated in any of various types of circuits including transistors as their components. Among other things, a significant flicker noise generated in a bias circuit, functioning as a basic element of an analog circuit, would affect every circuit supplied with a bias voltage or a bias current by the bias circuit. Thus, it is meaningful to reduce the noise of a bias circuit to a sufficiently low level.
Meanwhile, the flicker noise could be reduced by the use of transistors of an increased size. Nevertheless, an increase in the size of transistors leads to an increase in the overall chip area. In other words, use of transistors of an increased size causes an increase in costs. Also, in a current mirror circuit, for example, transistors on the input end often constitute a source of a non-negligible flicker noise. However, an increase in the size of those transistors would prevent the current mirror circuit from having a high mirror ratio and would require an increased amount of drain current to supply a predetermined amount of current to transistors on the output end, thus resulting in a considerable increase in power consumption.
U.S. Pat. No. 7,999,628 proposes a circuit configuration for a bias generation circuit having a relatively small area but having the ability to generate a low-noise bias voltage.
However, implementation of a bias generation circuit of the type disclosed in U.S. Pat. No. 7,999,628 requires, as one of its essential circuit components, a digital controller that carries out a predetermined procedure of control to determine the bias voltage. This leads to an increase in the number of design process steps to perform and/or an increase in the overall chip area.
In addition, generally speaking, a bias generating section controls the bias voltage by varying the resistance value of a variable resistor section. Thus, as the bias voltage is controlled, the impedance varies accordingly, which increases the chances of causing a variation in supply voltage and an error in voltage caused by such a variation. In addition, it is also difficult to increase the resolution sufficiently by defining a predetermined voltage range between the power supply and the ground to be the output range through division of the resistance.
Furthermore, when turned ON, a switch for controlling the resistance value of the variable resistor section allows a steady-state current to flow through it. Thus, CMOS transistors forming this switch would generate a flicker noise by themselves.
In view of the foregoing background, it is therefore an object of the present disclosure to provide a bias generator circuit which may generate a desired bias voltage or bias current using a simple configuration even without such a digital controller that carries out a predetermined procedure of control.